The present invention relates to a processor which receives a display video signal from a computer or the like and performs various sorts of processing operations over the signal according to specifications of a display device to display it on the display device.
A display video signal issued from an engineering workstation, a personal computer or a display terminal of a computer is output as a video signal of dots corresponding to picture elements or pixels on a display screen.
By converting the video signal into a digital signal and using a memory and an arithmetic operating circuit, the digital signal can be subjected to various processing operations including conversion of signal format of field frequency or aspect ratio and such image processing as enlargement/reduction (scaling), screen superposition or geometric transform. For example, when it is desired to form a 4-face multi-screen system in which 4 display devices are arranged adjacent to each other so that 2 of the 4 display devices are vertically in 2 stages and the remainder 2 are horizontally side by side and their 4 display screens are regarded as a single display screen; signals corresponding to 1/4 of an input video signal are subjected to a full-screen enlarging operation to display them at corresponding positions on the entire 4 screens. Thus, there can be arranged a display system which is large in scale and high in luminance and resolution.
Output signals issued from these digital signal processing circuits are supposed to be displayed on a display device of a so-called multi-scanning cathode-ray tube (CRT) type, so that horizontal scanning frequency fh, vertical scanning frequency fv, display line number, etc. will vary depending on the format of the input signals and such signal processing contents as enlargement.
In these years, display devices of the conventional cathode-ray tube (CRT) type have been replaced by display devices of liquid crystal, plasma, LED, etc. These display devices have an advantage over the cathode-ray tube type display device that they can be made dimensionally small in depth and thickness with less occupation space and can have a large display screen. These display devices, however, have a problem that a coordinate system for representing respective pixels is fixed and thus cannot be changed. That is, in the display device of the fixed pixel number type, the numbers of horizontal and vertical display pixels (also sometimes referred to as pixel numbers, hereinafter) are fixed so that it is difficult to directly display a signal not conforming to the pixel numbers on the display device without subjecting to any operation. More in detail, it has been difficult to directly display a signal having 480 effective lines or a signal having 1024 horizontal effective pixels and 768 effective lines on a display device having 1280 horizontal pixels and 1024 vertical pixels.
For this reason, when it is desired to correctly display a signal having a pixel number different from that of a display device of the fixed pixel number type, a signal processing circuit for changing such a pixel number is inevitably required. For example, when it is desired to display a signal having 640 horizontal effective pixels on a display device of 1024 pixels, it is necessary to display 8 pixels with use of the 5 pixels of an input signal (640: 1024=5: 8) and thus to generate display pixels through interpolating operation of the input pixels. As methods for interpolating the pixels of a one-dimensional signal, there are known such algorithms as previous-value hold interpolation based on one nearest point, linear interpolation based on near 2 points, and convolution interpolation based on near 4 points. When these algorithms are applied to horizontal and vertical respectively, it is possible to convert the pixel numbers of a two-dimensional image.
Examples of the arrangement of a signal processing circuit for performing such pixel interpolating operation are disclosed in JP-A-5-284334 and JP-A-5-328184.
When these signal processing operations are carried out together with the conversion of signal format of field frequency and aspect ratio and with image processing operations including enlargement/reduction (scaling), screen superimposition, and geometric transform; the numbers of horizontal and vertical pixels can be converted according to the display device for display thereon.
However, these pixel number converting operations are required to be carried out at a higher speed as the display device is increased in its resolution. For example, when it is desired to display 1280 horizontal effective pixels and 1024 effective lines with a frame frequency of 60 Hz, the dot clock becomes 100 MHz or more. For the purpose of realizing such a high speed signal processing operation that the dot clock exceeds 100 MHz, parallel processing operation is employed. The parallel processing operation is such that input pixels are separated into odd-numbered and even-numbered pixels, subjected to a converting operation to provide a double occupation time, and then are subjected to the parallel processing operation by 2 systems of processing circuits. In such a parallel processing system, it is highly difficult to perform arithmetic operation between adjacent pixel data, since pixels are processed as divided into odd-numbered and even-numbered pixel series.
Further, setting of an enlarging (reducing) factor (or scaling factor) requires data to be intermittently read out from a memory, but the data reading unit from the memory is limited by the number of parallel processing series (2 pixel units for the odd-numbered and even-numbered pixel series), which involves such a problem that it is impossible to freely set the enlarging (reducing) factor, thus making it difficult to perform the parallel processing operation.
For this reason, it becomes necessary to perform it with use of such a high-speed device as emitter coupled logic (ECL). However, this involves a problem that this increases power consumption and the heat generation caused by the increased power consumption makes it difficult to make the circuit small in size, with increased costs.
Further, when simplification of the interpolating algorithm and circuit leads to deterioration in the picture quality, it is difficult to provide a display device which can be made small in size with low costs and less power consumption to provide a high quality of picture.